I. INTRODUCTION
(page 1, col 2)
More sophisticated analyzing methods are needed to tighten the safety margins again
The approach presented here is a static timing analyzer considering aging (ASTA).
II. RELATED WORK
A. Transistor-level aging simulation
B. LUT-based aged gate model
A gate model provides gate performances Q (e.g., gate delay
τ ) as a function of input signals, output load CL and operating
conditions (temperature T, supply voltage VDD and process
P).
C. Estimation of aged gate delay
III. PROPOSED GATE MODEL
A canonical gate model provides the aged gate performance
for parameter drifts of individual transistors
A. Canonical gate model
B. Degradation equations
(page 3)
C. Calculation of duty factors
To calculate the drifts of a transistor, the duty factors
DFNBTI and DFHCI are needed
The following two stress conditions have to be fulfilled so
that a PMOS transistor M (e.g., PA in Fig. 1) is degraded due
to NBTI:
If condition A is fulfilled, it is sufficient that M’s source
is at the positive supply voltage VDD for condition B to be
fulfilled.
(p3 col 2)
The probability that both conditions A and B are fulfilled
also depends on the correlation of the gate input signals:
For a transistor M to be degraded due to HCI a considerable
current must flow in the channel, because the transistor is
demaged by accelerated carriers.
To obtain DFHCI , time tstress has to be expressed.
For calculating DFNBTI and DFHCI, the gate input signals
are important.
D. Gate model generation
